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d a t a sh eet product speci?cation supersedes data of 1995 mar 21 file under integrated circuits, ic02 1998 jul 03 integrated circuits TDA9840 tv and vtr stereo/dual sound processor with digital identification and i 2 c-bus control
1998 jul 03 2 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 features supply voltage 5 to 8 v de-emphasis source selector level and stereo matrix adjustment possible via the i 2 c-bus i 2 c-bus transceiver af inputs for nicam or am sound (standard l) af outputs for main and scart af input and output signals selectable via the i 2 c-bus information for identified transmission mode is readable via i 2 c-bus software is compatible with the tda8415/16/17 quartz oscillator and clock generator three digital pll, alignment-free two digital integrators, alignment-free stabilizer circuit for ripple rejection and constant output signals esd protection of all pins. general description the TDA9840 is a stereo/dual sound processor for tv and vtr sets. its identification ensures safe operation by using internal digital pll technique with extremely small bandwidth, synchronous detection and digital integration (switching time maximum 2.3 s; identification concerning the main functions). ordering information type number package name description version TDA9840 dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 TDA9840t so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1
1998 jul 03 3 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 quick reference data symbol parameter conditions min. typ. max. unit v p supply voltage (pin 18) 4.5 5 8.8 v i p supply current (pin 18) 15.5 16.5 20.5 ma v i(rms) nominal input signal voltage (v i1 , v i2 , v i3 ) (rms value) 54% modulation - 250 - mv v o(rms) nominal output signal voltage (rms value) thd 0.3% 54% modulation - 500 - mv v o(rms) clipping level of the output signal voltages (rms value) thd 1.5% v p = 5 v 1.4 1.6 - v v p = 8 v 2.4 2.65 - v d g v stereo control range for v i 1 (0.1 db steps) +2.4 +2.5 +2.6 db - 2.3 - 2.4 - 2.5 db level control range for v i 2 (0.5 db steps) +2.4 +2.5 +2.6 db - 1.9 - 2.0 - 2.1 db v i pil input voltage sensitivity of pilot frequency unmodulated 5 - 100 mv s/n(w) weighted signal-to-noise ratio ccir468-3 66 75 - db thd total harmonic distortion - 0.2 0.3 % t amb operating ambient temperature range 0 - +70 c f ident identi?cation window width normal mode stereo 2.0 - 2.0 hz dual 2.3 - 2.3 hz fast mode stereo 3.8 - 3.8 hz dual 5.8 - 5.8 hz t ident(on) total identi?cation time on normal mode stereo 0.35 - 2.3 s dual 0.35 - 2.0 s fast mode stereo 0.175 - 1.1 s dual 0.175 - 1.0 s v i tuner identi?cation voltage sensitivity - 28 - db m v d f pil pull-in frequency range of pilot pll f w = 10.008 mhz lower side - 296 -- 296 hz upper side 302 - 302 hz
1998 jul 03 4 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagrams a ndbook, full pagewidth TDA9840 mute level and stereo adjustment digital pll oscillator v i 1 digital pll and demodulator digital pll and demodulator digital integrator digital integrator generation of reference voltages i c-bus control 2 control logic 1 20 scl sda 11 12 13 14 main scart 500 mv rms 500 mv rms 500 mv rms 500 mv rms w 5 k w 5 k 15 17 9 10 10 nf 10 nf 10 k w 10 k w 40 k w 40 k w 7 8 250 mv rms (from 1st sc) 2.2 f 2.2 f 30 k w 47 pf 3.3 nf 2.5 mh 100 nf 10 f 10 nf 5 4 2 3 25 k w 25 k w v ref 19 6 18 16 100 f / 16 v 10 mhz dual bit stereo bit l r/b 250 mv rms l/a/mono 250 mv rms 2.2 f 2.2 f 500 mv rms 250 mv rms (from 2nd sc) c agc c lp c dcl c d1 c d2 1/2 v gnd xtal p v i 2 v i pil v o 1 v i 3 v i 4 v o 2 v o 3 v o 4 0 to 4.5 db stereo level v p c ref 10 k w - 2 db - 2 db 0 to 4.5 db 10 k w 0 to - 0.4 db a/mono 6 db 6 db 6 db 6 db w 25 k w 25 k w 25 k w 25 k power-on reset l+r 2 , a r, b 5% 5% q 0 = 70 tan d 0.002 mbe457 input and output levels are nominal values. they are related to the scart norm. (am: m = 0.54, fm: d f= 27 khz). fig.1 block diagram of the bipolar tv/vtr-stereo decoder.
1998 jul 03 5 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.2 block diagram of the bipolar tv/vtr-stereo decoder with fixed coil (alignment-free). o k, full pagewidth TDA9840 mute level and stereo adjustment digital pll oscillator v i 1 digital pll and demodulator digital pll and demodulator digital integrator digital integrator generation of reference voltages i c-bus control 2 control logic 1 20 scl sda 11 12 13 14 main scart 500 mv rms 500 mv rms 500 mv rms 500 mv rms w 5 k w 5 k 15 17 9 10 10 k w 10 k w 40 k w 40 k w 7 8 250 mv rms (from 1st sc) 2.2 f 2.2 f 27 k w 180 pf 1.8 nf 2% 4.7 mh 5% 100 nf 10 f 10 nf 5 4 2 3 25 k w 25 k w v ref 19 6 18 16 100 f / 16 v 10 mhz dual bit stereo bit l r/b 250 mv rms l/a/mono 250 mv rms 2.2 f 2.2 f 500 mv rms 250 mv rms (from 2nd sc) c agc c lp c dcl v i 2 v o 1 v i 3 v i 4 v o 2 v o 3 v o 4 0 to 4.5 db stereo level v p c ref 10 k w - 2 db - 2 db 0 to 4.5 db 10 k w 0 to - 0.4 db a/mono 6 db 6 db 6 db 6 db w 25 k w 25 k w 25 k w 25 k power-on reset l+r 2 , a r, b 10 nf c d1 5% 10 nf c d2 5% q 0 = 25 tan d 0.01 1/2 v gnd xtal p v i pil mbe458 input and output levels are nominal values. they are related to the scart norm. (am: m = 0.54, fm: d f= 27 khz). the components of the external lc band-pass filter have the following order-no.: philips germany only no: 4312 020 17525 or fastron sdn. bha., malaysia type smcc 472 j for l = 4.7 mhz ( 5%) philips components no: 2222 429 71802, c = 1.8 nf ( 2%) .
1998 jul 03 6 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 pinning symbol pin description sda 1 i 2 c-bus data input/output c agc 2 agc capacitor of pilot frequency ampli?er c lp 3 identi?cation low-pass capacitor c dcl 4 dc loop capacitor v i pil 5 pilot frequency input voltage c ref 6 capacitor of reference voltage ( 1 2 v p ) v i 1 7 af input signal v i1 (from 1st sound carrier) v i 2 8 af input signal v i 2 (from 2nd sound carrier) v i 3 9 af input signal v i 3 (nicam or am sound (standard l)) v i 4 10 af input signal v i 4 (nicam) v o 4 11 af output signal v o 4 (scart) v o 3 12 af output signal v o 3 (scart) v o 2 13 af output signal v o 2 (main) v o 1 14 af output signal v o 1 (main) c d1 15 50 m s de-emphasis capacitor of af channel 1 gnd 16 ground (0 v) c d2 17 50 m s de-emphasis capacitor of af channel 2 v p 18 supply voltage (+5 to +8 v) xtal 19 10 mhz crystal input scl 20 i 2 c-bus clock input fig.3 pin configuration. f page TDA9840 mbe459 1 2 3 4 5 6 7 8 9 10 sda c c c v c v v v 20 19 18 17 16 15 14 13 12 11 scl xtal v c gnd c v v agc lp dcl i pil ref i 1 i 2 i 3 v i 4 p d2 d1 o 1 o 2 v v o 3 o 4
1998 jul 03 7 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 functional description the TDA9840 (see fig.1) receives the signals from the fm-demodulators in a tv two sound-carrier system. the circuit is realized by the h00485 bipolar process. the ic is intended for use in economic tv and vtr receivers. therefore optimum relationship between integration of functions and use of external components has been striven for. additionally a new type of identification circuit has been developed. af signal handling the input af signals, derived from the two sound carriers, are processed in analog form using operational amplifiers.the circuit incorporates level- and stereo-adjustment to correct the spreading in the fm detector output levels. dematrixing uses the technique of two amplifiers processing the af signals. finally, a source selector provides the facility to route the mono signal through to the outputs (forced mono). de-emphasis is performed by two rc low-pass filter networks with internal resistors and external capacitors. this provides a frequency response with the tolerances given in fig.4. a source selector, controlled via the i 2 c-bus, allows selection of the different modes of operation in accordance with the transmitted signal. the device was designed for a nominal input signal (fm: 54% modulation is equivalent to d f= 27 khz / am: m = 0.54) of 250 mv rms (v i1 ,v i2 ), respectively 500 mv rms (v i3 ,v i4 ). a nominal gain of 6 db for v i1 and v i2 signals and 0 db for v i3 and v i4 signals is built-in. by using rail-to-rail operational amplifiers, the clipping level (thd 1.5%) is 1.6 v rms for v p = 5 v and 2.65 v rms for v p = 8 v at outputs v o1 , v o2 ,v o3 and v o4 . care has been taken to minimize switching plops. also total harmonic distortion and random noise are considerably reduced. identi?cation the pilot signal is fed via an external rc high-pass filter and single tuned lc band-pass filter to the input of a gain controlled amplifier. the external lc band-pass filter in combination with the external rc high-pass filter should have a loaded q-factor of about 40 to 50 to ensure the highest identification sensitivity. by using a fixed coil ( 5%) to save the alignment (see fig.2), a q-factor of about 12 is proposed. this may cause a loss in sensitivity of about 2 to 3 db. a digital pll circuit generates a reference carrier, which is synchronized with the pilot carrier. this reference carrier and the gain controlled pilot signal are fed to the am-synchronous demodulator. the demodulator detects the identification signal, which is fed through a low-pass filter with external capacitor c lp (pin 3) to a schmitt-trigger for pulse shaping and suppression of low level spurious signal components. this is a measure against mis-identification. the identification signal is amplified and fed through an agc low-pass filter with external capacitor c agc (pin 2) to obtain the agc voltage for controlling the gain of the pilot signal amplifier. the identification stages consist of two digital pll circuits with digital synchronous demodulation and digital integrators to generate the stereo or dual sound identification bits which can be read out via the i 2 c-bus. a 10 mhz quartz crystal oscillator provides the reference clock frequency. the corresponding detection bandwidth is larger than 50 hz for the pilot carrier signal, so that f p -variations from the transmitter can be tracked in case of missing synchronisation with the horizontal frequency f h . however the detection bandwidth for the identification signal is made small (approximately 1 hz) to reduce mis-identification. figure 2 shows an example of the alignment-free f p band-pass filter. to achieve the required q l of approximately 12, the q 0 at f p of the coil was chosen to be approximately 25 (effective q 0 including pcb influence). using coils with other q 0 , the rc-network (r fp ,c fp ) has to be adapted accordingly. it is assumed that the loss factor tan d of the resonance capacitor is 0.01 at f p . copper areas under the coil might influence the loaded q and have to be taken into account. care has also to be taken in environments with strong magnetic fields when using coils without magnetic shielding. i 2 c-bus transceiver the complete ic is controlled by a microcomputer via the i 2 c-bus. the built-in i 2 c-bus transceiver transmits the identification result to the i 2 c-bus and receives the control data for the source selector and level control. the i 2 c-bus protocol is given in tables 2 to 12 respectively. the data transmission between the microcontroller and the other i 2 c-bus controlled ics is not disturbed, when the supply voltage of the TDA9840 is not connected or when powering up or down. finally, a schmitt-trigger is built-in the sda/scl interface to suppress spikes from the i 2 c-bus.
1998 jul 03 8 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 power supply the different supply voltages and currents required for the analog and digital circuits are derived from an internal band-gap reference circuit. the af reference voltage is 1 2 v p . for a fast setting to 1 2 v p an internal start-up circuit is added. a good ripple rejection is achieved with the external capacitor c ref = 100 m f/16 v in conjunction with the high ohmic input of the 1 2 v p pin (pin 6). additional dc-load on this pin is prohibited. power-on reset when a power-on reset is activated by switching on the supply voltage or because of a supply voltage breakdown, the 117/274 hz dpll, the 117/274 hz integrator and the registers will be reset. both af channels (main and scart) are muted. fast mode / test mode the TDA9840 has a fast mode (test mode) to reduce the integration time of the 117/274 hz integrator from approximately 1 to 0.5 s. esd protection all pins are esd protected. the protection circuits represent the latest state of the art. internal circuit the internal pin loading diagram is given in fig.7. limiting values in accordance with the absolute maximum rating system (iec 134). note 1. charge device model class b: discharging a 200 pf capacitor through a 0 w series resistor. thermal characteristics symbol parameter conditions min. max. unit v p supply voltage (pin 18) - 0.3 10 v v i voltage at pins 1 and 20 - 0.3 5.5 v v i voltage at pins 2 to 15, 17 and 19 - 0.3 v p v t stg storage temperature - 25 +150 c t amb operating ambient temperature 0 +70 c v esd electrostatic handling for all pins note 1 - 300 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air dip20 73 k/w so20 90 k/w
1998 jul 03 9 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 characteristics v p =5v; t amb = +25 c; nominal input signal v i1,2 = 0.25 v rms value (fm: 54% modulation is equivalent to d f= 27 khz); nominal input signal v i3,4 = 0.5 v rms value (am: m = 0.54); nominal output signal v o1,2,3,4 = 0.5 v rms value; f af = 1 khz; v i pil = 16 mv rms value; f pil = 54.6875 khz (identi?cation frequencies: stereo = 117.48 hz, dual = 274.12 hz), 50 m s pre-emphasis; noise measurement in accordance with ccir468-3 , working oscillator frequency f w = 10.008 mhz; currents into the ic positive; measured in test circuit according to fig.5; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v p supply voltage (pin 18) 4.5 5 8.8 v i p supply current (pin 18) 15.5 16.5 20.5 ma p tot total power dissipation 69.75 82.5 180.4 mw v n(dc) dc voltage (pins 7 to 15 and 17) 1 2 v p - 0.1 1 2 v p 1 2 v p + 0.1 v v ref(dc) dc reference voltage (pin 6) 1 2 v p - 0.1 1 2 v p 1 2 v p + 0.1 v l l(dc) dc leakage current (pin 6) -- 1 m a af inputs; v i1 and v i2 (pins 7 and 8) v i(rms) nominal input signal voltage (rms value) 54% modulation - 0.25 - v v i(rms) clipping voltage level (rms value) thd 1.5%; note 1 v p = 5 v 0.625 0.715 - v v p = 8 v 1.050 1.200 - v thd 1.5%; note 2 v p = 5 v 0.780 0.900 - v v p = 8 v 1.300 1.500 - v g v af signal voltage gain g = v o /v i ; note 3 5 6 7 db d g v (v o1 ) stereo control range only at pin 7 +2.4 +2.5 +2.6 db - 2.3 - 2.4 - 2.5 db nominal step maximum 49 steps - 0.1 - db d g v (v o2 ) level control range only at pin 8 +2.4 +2.5 +2.6 db - 1.9 - 2.0 - 2.1 db nominal step maximum 9 steps - 0.5 - db r i input resistance 40 50 60 k w r deem internal de-emphasis resistor (pins 15 and 17) see fig.4 4.25 5.0 5.75 k w additional af input pin (pins 9 and 10) v i(rms) nominal input signal voltage (rms value) 54% modulation - 0.5 - v v i(rms) clipping voltage level (rms value) thd 1.5% v p = 5 v 1.25 1.40 - v v p =8v 2.10 2.35 - v g v af signal voltage gain g=v o /v i ; note 3 - 10 1 db r i input resistance 40 50 60 k w
1998 jul 03 10 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 af outputs (pins 11 to 14) v o(rms) nominal output signal voltage (rms value) thd 0.3%; 54% modulation - 0.5 - v v o(rms) clipping voltage level (rms value) thd 1.5% v p = 5 v 1.4 1.6 - v v p = 8 v 2.4 2.65 - v r o output resistance 150 250 350 w c l load capacitor on output -- 1.5 nf r l load resistor on output (ac-coupled) 10 -- k w b frequency response (bandwidth) f i = 40 to 20000 hz; note 4 - 0.5 - +0.5 db b - 3db frequency response - 3 db; note 4 300 350 400 khz thd total harmonic distortion note 3 - 0.2 0.3 % s/n(w) weighted signal-to-noise ratio ccir468-3 (quasi-peak) 66 75 - db a cr crosstalk attenuation for notes 3 and 5 dual ? z s ? 1k w 70 75 - db stereo ? z s ? 1k w 40 45 - db a mute mute attenuation ? z s ? 1k w ; note 3 76 80 - db d v dc change of dc level output voltage between any two modes of operation after switching -- 10 mv psrr power supply ripple rejection f r = 70 hz; see fig.6 50 65 - db i o(dc) dc output current -- 20 m a a i2c noise from i 2 c-bus note 6 - 90 80 db 10 mhz crystal oscillator (pin 19) f r series resonant frequency of crystal (fundamental mode) c l = 20 pf 9.995 10.008 10.021 mhz f w working oscillator frequency (running in parallel resonance mode) over operating temperature range including ageing and in?uence of drive circuit 9.988 10.008 10.028 mhz r r equivalent crystal series resistance even at extremely low drive level (<1 pw) over operating temperature range with c 0 =6pf - 60 200 w r n crystal series resistance of unwanted mode 2 r r -- w c 0 crystal parallel capacitance with r r 100 w- 610pf c 1 crystal motional capacitance - 25 50 ff symbol parameter conditions min. typ. max. unit
1998 jul 03 11 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 p xtal level of drive in operation -- 5 m w v osc(p-p) oscillator operating voltage (peak-to-peak value) 500 550 600 mv pilot processing v i pil(rms) pilot input voltage level at pin 5 (rms value) unmodulated 5 - 100 mv r i pil pilot input resistance 500 1000 - k w m modulation depth am 25 50 75 % d f pil pilot pll pull-in frequency range (referred to f pil = 54.6875 khz) f w = 9.988 mhz lower side - 405 -- 405 hz upper side 192 - 192 hz f w = 10.008 mhz lower side - 296 -- 296 hz upper side 302 - 302 hz f w = 10.028 mhz lower side - 188 -- 188 hz upper side 411 - 411 hz t pil pilot pll pull-in time 0 - 1.7 ms f lp low-pass frequency response - 3 db 450 600 750 hz r 3 low-pass output resistance 18.75 25 31.25 k w v 4(rms) identi?cation threshold voltage (rms value) -- 70 mv q l loaded quality factor of resonance circuit high sensitivity 40 - 50 loaded quality factor of resonance circuit with ?xed coil sensitivity loss 2 to 3 db; see fig.2 - 12 - t acqui agc agc acquisition time v i pil(rms) switched from 0 to 100 mv rms value -- 0.1 s identi?cation (internal functions) v i tuner identi?cation voltage sensitivity (pin 5) note 7 - 28 - db m v c/n pilot carrier-to-noise ratio for start of identi?cation note 8 - 33 - db/hz h hysteresis note 7 -- 2db symbol parameter conditions min. typ. max. unit
1998 jul 03 12 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 f det pull-in frequency range of identi?cation pll (referred to f det stereo = 117.48 hz and f det dual = 274.12 hz) normal mode lower side stereo - 0.38 -- 0.38 hz dual - 0.69 -- 0.69 hz normal mode upper side stereo 0.69 - 0.69 hz dual 0.69 - 0.69 hz fast mode lower side stereo - 0.89 -- 0.89 hz dual - 2.05 -- 2.05 hz fast mode upper side stereo 1.15 - 1.15 hz dual 2.05 - 2.05 hz t det pull-in time of identi?cation pll (referred to f det stereo = 117.48 hz and f det dual = 274.12 hz) normal mode stereo 0 - 1.35 s dual 0 - 0.72 s fast mode stereo 0 - 0.57 s dual 0 - 0.25 s f ident identi?cation window frequency width (referred to f det stereo = 117.48 hz and f det dual = 274.12 hz) normal mode; note 9 stereo 2.0 - 2.0 hz dual 2.3 - 2.3 hz fast mode; note 9 stereo 3.8 - 3.8 hz dual 5.8 - 5.8 hz t integr integrator time constant normal mode 0.94 - 0.94 s fast mode 0.47 - 0.47 s t ident(on) total identi?cation time on normal mode; note 10 stereo 0.35 - 2.3 s dual 0.35 - 2.0 s fast mode; note 10 stereo 0.175 - 1.1 s dual 0.175 - 1.0 s t ident(off) total identi?cation time off normal mode; note 11 stereo 0.6 - 1.6 s dual 0.6 - 1.6 s fast mode; note 11 stereo 0.3 - 0.8 s dual 0.3 - 0.8 s symbol parameter conditions min. typ. max. unit
1998 jul 03 13 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 notes 1. input control amplifiers with d g v = 0 db. 2. input control amplifiers with d g v = - 2 db. 3. v o = 0.5 v rms value; f = 1 khz; input control amplifiers with d g v = 0 db. 4. without de-emphasis capacitors with respect to nominal gain. 5. in dual mode: a (b)-signal into b (a) channel. in stereo mode: r-signal into left channel; l-signal = 0. 6. test procedure tbf (same as tda9855). 7. tuner input signal, measured with pcalh reference front end ( 1 2 emf, 75 w , 2t/20t/white bar, 100% video) and pc/sc 1 = 13 db; pc/sc 2 = 20 db. the pilot band-pass has to be aligned. 8. bandwidth of the pilot bp-filter b - 3db = 1.2 khz. v i2 input driven with identification-modulated pilot carrier and white noise. 9. identification window is defined as total pull-in frequency range (lower plus upper side) of identification pll (steady detection) plus window increase due to integrator (fluctuating detection). 10. the maximum total system identification time on is equal to t ident(on) plus t acqui agc plus t i2c read-out . 11. the maximum total system identification time off is equal to t ident(off) plus t i2c read-out . i 2 c-bus transceiver (pins 1 and 20) f ci clock frequency 0 - 100 khz i 2 c-bus: scl (pin 20) v il low level input voltage - 0.3 - 1.5 v v ih high level input voltage 3.0 - 5.5 v t low timing low period 4.7 -- m s t high timing high period 4.0 -- m s t r rise time -- 1 m s t f fall time -- 0.3 m s i il low level input current --- 10 m a i ih high level input current -- 10 m a i 2 c-bus: sda (pin 1) v il low level input voltage - 0.3 - 1.5 v v ih high level input voltage 3.0 - 5.5 v t r rise time -- 1 m s t f fall time -- 0.3 m s t su data set-up time 0.25 -- m s i il low level input current --- 10 m a i ol low level output current - 3 -- ma i ih high level input current -- 10 m a symbol parameter conditions min. typ. max. unit
1998 jul 03 14 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 i 2 c-bus protocol for the tv and vtr stereo/dual sound processor TDA9840 the TDA9840 has an i 2 c-bus interface with five registers: status, test, switch, level and stereo adjustment register controlled by a microcontroller via i 2 c-bus. the status register can be read and the other registers are write registers. the status byte represents the transmitter status detected by the identification circuit and the power-on reset status. the switch register controls the source selectors of the af signal part, and the level and stereo adjustment register set the input level and stereo adjustment stage. additionally, a test register is built-in to reduce the detection time of the identification circuit (test mode, fast mode respectively). i 2 c-bus transceiver and data-handling (bus speci?cation) the TDA9840 is controlled by a microcomputer via the bidirectional 2-line i 2 c-bus. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. when the bus is free, both lines are high. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change, when the clock signal on the scl line is low. the set-up and hold times are specified in the chapter characteristics. a high-to-low transition of the sda line, while scl is high, is defined as the start condition. a low-to-high transition of the sda line, while scl is high, is defined as the stop condition. the bus transceiver will be reset on the reception of a start condition. the bus is considered to be busy after the start condition. the bus is considered to be free again after a stop condition. data format transmitter mode for the data transmission no subaddress is to be transmitted, because there is only one read register implemented. so the total number of bytes reduces from three to two. the second byte represents the status of the ic. status register (see table 4) the bit d7 (ponres) represents the status of the ic and indicates whether the power-on reset was activated by switching-on the supply voltage or a supply voltage breakdown. if so, the i 2 c-bus transceiver, the digital plls and integrators are initialized and the ponres bit is set to high. after a successful reading of the status register, the bit d7 will be reset to low. the bits d5 and d6 represent the transmitter status detected by the identification circuit (stereo, dual or mono transmission). the other bits are set to 0 (default). data format for the receiver table 1 registers for receiver mode (see table 6) the port register is without function, because this ic has no control ports as tda8415/6/7. a data byte for the subaddress (01) hex will not be stored in any register. an acknowledge will be sent to the microcontroller. the first byte of the data transmission is the slave address and the second byte is the subaddress indicating the data register in which the data shall be stored. starting from subaddress (00) hex the n-th data byte will automatically be stored under subaddress n - 1. all 8 bits of the subaddress are decoded by the device. the subaddresses from (04) hex to (ff) hex are forbidden for the user. if the i 2 c-bus transceiver receives subaddresses from (05) hex to (ff) hex , no acknowledge will be sent back to the microcontroller. switch register the source selector is controlled by the switch register. table 7 shows the modes of operation. note, that in the event of the external operation mode, no further selection is possible. register value switch register (00) hex port register (01) hex (without function) level adjustment register (02) hex stereo adjustment register (03) hex test register (04) hex
1998 jul 03 15 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 level adjustment register the information about the level adjustment of the af channel v i 2 (pin 8) is stored in the level adjustment register (see table 10). there are 10 steps (positions) of the af level adjustment stage. the level range is from 2.5 db up to - 2.0 db in 0.5 db steps. after a power-on reset, the data byte of the level adjustment register will be set to (00) hex : 0 db gain at the af input v i 2 . stereo adjustment register the information about the stereo adjustment of the af channel v i 1 (pin 7) is stored in the stereo adjustment register (see table 11). there are 50 steps (positions) of the af stereo adjustment stage. the stereo range is from 2.5 db up to - 2.4 db in 0.1 db steps. after a power-on reset, the data byte of the stereo adjustment register will be set to (00) hex : 0 db gain at the af input v i1 . test register (also used for fast mode) table 12 shows the meaning of the test register. the integration time of the integrator is approximately 1 s (normal mode, default). if the data byte of this register is set to high, the integration time is reduced from approximately 1 to approximately 0.5 s (fast mode, test mode). the pull-in ranges of the identification plls are changed to: stereo: - 0.89/+1.15 hz dual: 2.05 hz. if the integration time of the integrator is switched from one mode to the other (i.e. from fast mode/test mode to normal mode), the status register bits d5 and d6 might set to zero internally (mono). therefore, the previous status register information has to be stored by the microcontroller until the transmitter status is detected again by the identification circuit (now in the new mode) the first time. the data byte of the test register can be reset in two different ways to (00) hex : integration time approximately 1 s, normal mode: after a power-on reset, for instance by switching the power supply v p off and on again data transmission via i 2 c-bus for the test register (see table 12). level and stereo adjustment for the level and stereo adjustment of both af channels v i1 and v i2 , the following procedure will be recommended. level adjustment of the af channel v feeds af signal at the input v i 2 sets the data byte of the switch register (dual mode) to (1a) hex measures the signal at the outputs v o2 or v o4 adjusts the output level with the level adjustment register. stereo adjustment of the af channel v i 1 feeds af stereo signals at the inputs v i1 ((l+r)/2) and v i2 (r) sets the data byte of the switch register (stereo mode) to (2a) hex measures the crosstalk attenuation between v o1 and v o2 or v o3 and v o4 adjusts the crosstalk attenuation with the stereo adjustment register. during the stereo adjustment the data byte of the level adjustment register does not change. after the level and stereo adjustment, the bytes of the level and stereo adjustment register must be stored by the microcontroller in a memory. (to avoid mis-adjustment it would be wise to compare the stored bytes with the proper adjustment bytes). if the ponres bit of the status register will be set to high (see status register) the data bytes for these both registers must be sent out of the memory to the TDA9840 via i 2 c-bus. also the data byte of the switch register (see table 7) must be changed, because the af outputs are muted.
1998 jul 03 16 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 i 2 c-bus format x is the read/write control bit; x = 0, order to write (the circuit is slave receiver); x = 1, order to read (the circuit is slave transmitter). if more than 1 byte of data is transmitted, then auto-increment of the significant subaddress is performed. table 2 i 2 c-bus; slave address/subaddress/data format table 3 explanation of table 2 table 4 i 2 c-bus; slave address/data to read the status byte (x = 1 in the address byte) table 5 explanation of table 4 s slave address a subaddress a data p bit function s start condition slave address 1000 010x a acknowledge, generated by the slave subaddress dual sound a/b data data byte; see table 6 p stop condition function slave address data d7 d6 d5 d4 d3 d2 d1 d0 status byte 1000 0101 ponres st ds 00000 bit function ponres = 0 after a successful reading of the status register ponres = 1 after power-on reset or after supply breakdown st = 0; ds = 0 mono sound identified st = 0; ds = 1 dual sound identified st = 1; ds = 0 stereo sound identified st = 1; ds = 1 incorrect identification
1998 jul 03 17 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 table 6 i 2 c-bus; subaddress/data for writing (x = 0 in the address byte) note 1. this byte is acknowledged by the TDA9840. function of the bits: sw6 to sw0 input and output af selection; see table 7 lv3 to lv0 level adjustment; see table 10 st5 to st0 stereo adjustment; see table 11. table 7 data byte to select af inputs and af outputs [subaddress (00) hex ] function subaddress data d7 d6 d5 d4 d3 d2 d1 d0 switching 0000 0000 0 sw6 sw5 sw4 sw3 sw2 sw1 sw0 without function (note 1) 0000 0001 00000000 level adjustment 0000 0010 0000lv3lv2lv1lv0 stereo adjustment 0000 0011 0 0 st5 st4 st3 st2 st1 st0 transmission mode input signal output signal data st/ds/m ext main scart v i1 pin 7 v i2 pin 8 v i3 pin 9 v i4 pin 10 v o1 pin 14 v o2 pin 13 v o3 pin 12 v o4 pin 11 d7 d6 d5 d4 d3 d2 d1 d0 hex sound mute ----- no signal 0 0 0 0000000 mono m m --- mmmm0001000010 stereo st s r -- ssss0001000010 sr -- lrlr001010102a dual ds a b -- abaa0001001012 ab -- abab000110101a ab -- abba0001011016 ab -- abbb000111101e external --- cdcdcd011110107a table 8 explanation of table 7 signal description r right l left s a and b dual sound a/b lr + () 2 -------------------- c nicam or am sound (standard l) d nicam m mono sound ds dual sound st stereo sound signal description
1998 jul 03 18 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 table 9 af switch con?guration table 10 data byte to select level adjustment [subaddress (02) hex ] input output transmitter status signal main scart mono m mm mm stereo l l or m l or m r r or m r or m dual a a a or b b b a or b external c c c ddd d g v (db) data d7 d6 d5 d4 d3 d2 d1 d0 hex +2.5 0 0 0 0 1 1 0 1 0d +2.0 0 0 0 0 1 1 0 0 0c +1.5 0 0 0 0 1 0 1 1 0b +1.0 0 0 0 0 1 0 1 0 0a +0.5 0 0 0 0 1 0 0 1 09 0 0000000000 - 0.5 0000000101 - 1.0 0000001002 - 1.5 0000001103 - 2.0 0000010004
1998 jul 03 19 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 table 11 data byte to select stereo adjustment [subaddress (03) hex ] d g v (db) data d7 d6 d5 d4 d3 d2 d1 d0 hex +2.5 0 0 1 1 1 0 0 1 39 +2.4 0 0 1 1 1 0 0 0 38 +2.3 0 0 1 1 0 1 1 1 37 +2.2 0 0 1 1 0 1 1 0 36 +2.1 0 0 1 1 0 1 0 1 35 +2.0 0 0 1 1 0 1 0 0 34 +1.9 0 0 1 1 0 0 1 1 33 +1.8 0 0 1 1 0 0 1 0 32 +1.7 0 0 1 1 0 0 0 1 31 +1.6 0 0 1 1 0 0 0 0 30 +1.5 0 0 1 0 1 1 1 1 2f +1.4 0 0 1 0 1 1 1 0 2e +1.3 0 0 1 0 1 1 0 1 2d +1.2 0 0 1 0 1 1 0 0 2c +1.1 0 0 1 0 1 0 1 1 2b +1.0 0 0 1 0 1 0 1 0 2a +0.9 0 0 1 0 1 0 0 1 29 +0.8 0 0 1 0 1 0 0 0 28 +0.7 0 0 1 0 0 1 1 1 27 +0.6 0 0 1 0 0 1 1 0 26 +0.5 0 0 1 0 0 1 0 1 25 +0.4 0 0 1 0 0 1 0 0 24 +0.3 0 0 1 0 0 0 1 1 23 +0.2 0 0 1 0 0 0 1 0 22 +0.1 0 0 1 0 0 0 0 1 21 0 00000000 00 - 0.100000001 01 - 0.200000010 02 - 0.300000011 03 - 0.400000100 04 - 0.500000101 05 - 0.600000110 06 - 0.700000111 07 - 0.800001000 08 - 0.900001001 09 - 1.0000010100a - 1.1000010110b - 1.2000011000c - 1.3000011010d - 1.4000011100e - 1.500001111 0f - 1.600010000 10 - 1.700010001 11 - 1.800010010 12 - 1.900010011 13 - 2.000010100 14 - 2.100010101 15 - 2.200010110 16 - 2.300010111 17 - 2.400011000 18 d g v (db) data d7 d6 d5 d4 d3 d2 d1 d0 hex table 12 data byte to select integration time [subaddress (04) hex ] function of the bits: intfu = 0 integrator function enabled intfu = 1 integrator function disabled int1sn = 0 integration time approximately 1 s (default) int1sn = 1integration time approximately 0.5 s. function subaddress data d7 d6 d5 d4 d3 d2 d1 d0 test byte 0000 0100 xxxxxx intfu int1sn
1998 jul 03 20 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 fig.4 tolerance scheme of af frequency response; de-emphasis with c d1 , c d2 = 10 nf ( 5%), r internal =5k w ( 15%). - 2 + 1 + 2 - 1 10 5 med647 10 4 10 3 10 2 10 0 v oaf (db) f oaf (hz) r: - 15%; c: - 5% r: + 15%; c: + 5%
1998 jul 03 21 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 handbook, full pagewidth mbe460 TDA9840 10 m f c agc 1 2 3 4 5 6 7 8 9 10 sda 3.3 nf 2.5 mh c lp c ref c dcl 10 nf 100 nf 1/2 v p 2.2 m f 2.2 m f 2.2 m f 47 pf 30 k w v i 2 v i 1 v i 3 af from 5.5 mhz af from 5.742 mhz from external sound source c 2.2 m f v i 4 from external sound source d 20 19 18 17 16 15 14 13 12 11 v o 4 v o 3 scart v o 2 v o 1 main 50 m s de-emphasis 5% c d2 10 nf 50 m s de-emphasis 5% c d1 10 nf 10 m f c vp v p 10 mhz xtal scl 100 m f/16 v fig.5 test circuit of the stereo decoder TDA9840. fig.6 test circuit for measurement of ripple rejection. handbook, full pagewidth 100 f / 16 v TDA9840 100 f 6 7 8 9 10 16 18 w 5 v modulated with 200 mv (p-p) 70 hz 100 f 10 k v b v p 11 12 13 14 measurements on outputs v o 1 o 2 o 3 o 4 v v v mbe462
1998 jul 03 22 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 internal circuitry fig.7 internal circuits. handbook, full pagewidth w 2 k + + 25 k w + 1 2 3 68 a 40 a + 5 k w 5 k w 40 a + 60 a 4 5 1/2 v p 1/2 v p 1/2 v p 1/2 v p 1/2 v p 6 i 7 i b 8 i b 9 i b 10 i b b 5 k w 2 k w + + 5 k w 3 pf 13 k w 20 19 18 + + 5 k w 17 16 + + 5 k w 15 + 200 a + 200 a + 200 a + 200 a 14 13 12 11 TDA9840 af outputs af inputs v p gnd sda c agc c lp c dcl v i pil c ref v i 1 v i 2 v i 3 v i 4 v o 1 v o 2 v o 3 v o 4 c d1 c d2 scl xtal 25 k w ? db 22.5 k w 25 k w + 10 k w 40 k w 10 k w ? db 40 k w 25 k w ? db 25 k w 25 k w ? db 25 k w + + +5 v esd protection diode for pins 2 to 15, 17 and 19 zener diode protection for pins 1, 18 and 20 v p 5 k w mbe461
1998 jul 03 23 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 92-11-17 95-05-24 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.0 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.078 0.17 0.020 0.13 sc603 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
1998 jul 03 24 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013ac pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 95-01-24 97-05-22
1998 jul 03 25 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 jul 03 26 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1998 jul 03 27 philips semiconductors product speci?cation tv and vtr stereo/dual sound processor with digital identi?cation and i 2 c-bus control TDA9840 notes
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+41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/00/03/pp28 date of release: 1998 jul 03 document order number: 9397 750 03999

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